1. Field of the Invention
The present invention relates, in general, to a method for fabricating a highly integrated semiconductor memory device and, more particularly, to a method for the fabrication of a semiconductor memory device, capable of securing a high charge storage capacity under the reduction of memory cell dimension.
2. Description of the Prior Art
An ordinary semiconductor memory device such as direct random access memory (hereafter referred to as "DRAM") has difficulty in securing a sufficient charge storage capacity as it is highly integrated. This is because the surface area of a storage electrode as well as the area occupied by a memory cell is largely reduced with the high integration of a semiconductor memory device. In fact, since a storage electrode 11 constituting a memory cell along with a field effect transistor, as shown in FIG. 1, is structured to have a flat board shape over the field effect transistor, its surface area is largely reduced with the reduction of the area occupied by a memory cell. Conventional memory cell fabrication methods also cannot increase the surface area of a storage electrode because the storage electrode is formed in the shape of a flat board thereby.
In order to better understand the background of the present invention, a description will now be given together with one of the conventional structure of a semiconductor memory device.
Referring to FIG. 1, a cross section of the semiconductor device is shown having a conventional semiconductor memory structure. As shown in FIG. 1, a semiconductor substrate 1 is sectioned by a field oxide film 2 into an isolation region and a device region over which a gate insulating film 3 and a word line is formed, followed by the formation of an oxide film spacer at a side wall of the word line 4. Using the word line and the spacer as a mask, dopants are implanted into the semiconductor substrate 1, to form a source/drain region 6, 6'. As a result, a transistor is fabricated. Thereafter, an insulating film 7 for planarization is coated over the entire surface of the transistor, which is then covered with a storage electrode 9 in such a way as to make the storage electrode 9 contact with the source or drain region. Finally, a dielectric film 18 is formed on the storage electrode 9, followed by the formation of a plate electrode 19 on the dielectric film 18.
As mentioned above, since the conventional semiconductor memory device has a flat board-type storage electrode, it cannot secure a sufficient charge storage capacity with the reduction of an area occupied by memory cell. The insufficient security of charge storage capacity incapacitates high integration in the conventional semiconductor memory device.